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Aspiration Statement
“Aspiring to innovate in robotics, embedded systems, and RTL design verification. Passionate about developing efficient automation solutions, optimizing hardware-software co-design, and advancing verification methodologies for high-performance computing and control systems”
Core Skills
- Aerial Robotics
- Computer Vision in Python
- System Verilog
- Zephyr RTOS
Experience
Leadership / Meta-curricular
- Participant, Invent for the Planet
Internship / Volunteer Work
- Verification Engineer Intern, Impare (March – June 2025)
Final Year Project
Project Title
UVM-Based Design Verification of Risc-V I-extension - Comprehensive Guide
Description
This project focuses on developing a structured verification environment using Universal Verification Methodology (UVM) to validate the integer instruction set extension of a RISC-V core. The project involves creating testbenches, writing constrained-random test cases, and analyzing functional coverage to ensure compliance with the RISC-V ISA specifications. the project focuses on creating a comprehensive guide for the upcoming batches to have a hands-on experience in UVM based verification, completely based on the use of open-source tools, given that industry-grade tools are licensed and expensive, while open-source/free tools lack documentation and proper guidance.